In a modulator for digital mobile telecommunication, the pulse shaping interpolation filtering is required in order to prohibit an inter-symbol interference at the rear end of the modulator. Specially, in case of an IMT-2000 synchronous terminal modulator as a next-generation mobile communication system, as a 1-bit output of four channels is multiplied by a gain within a single chip, channels are added two by two and result are experienced by OCQPSK modulation, two FIR filters having n-bit input are required.
FIG. 1 illustrates a construction of an OCQPSK modulating device specified in an IMT-2000 synchronous terminal rule to which the present invention is applied. The OCQPSK modulating device is mainly consisted of an OCQPSK modulating block and a FIR filter block, which are consisted of a Walsh covering stage for discriminating four channels, a gain stage for adjusting gains of respective channels, a channel adder, an OCQPSK modulating stage and a FIR filter for pulse shaping.
Explaining in more detail, 1-bit input of four channels CH1, CH2, CH3 and CH4 is Walsh-covered by Walsh quadrature codes Walsh2, Walsh3 and Walsh410 for by means of exclusive-OR gates 11, 12 and 13 for channel discrimination. Next, the 1-bit input is inputted to the gain stage 20 in which the gains G1, G2, G3 and G4 of respective channels are multiplied by means of the multipliers 21, 22, 23 and 24, in order to adjust gains of respective channels for channel discrimination. Then, the outputs of n-bits type from the gain stage are added two by two in the adders 31 and 32 in the channel adder 30, thereby producing two quadrature signals DI and DQ.
These two quadrature DI and DQ signals are modulated in the OCQPSK modulator 40. The OCQPSK modulator 40 includes a PN spreader 41 using PN sequence generated in a long & short PN generator 49, a complex adder 42 for performing a complex multiplication for the PN sequence based on an OCQPSK modulation scheme, multipliers 43, 44, 45 and 46, and adders 47 and 48. The outputs from the OCQPSK modulator 40 are inputted, in a n-bit type, to FIR filter 50. The FIR filter 50 is consisted of two FIR filter 51 and 52 each having n-bits inputs for pulse shaping, where the outputs of n-bits type are FIR-filtered. The output signals from the two FIR filters 51 and 52 are then inputted to D/A converters 60 and 61 of an analog chip, modulated 62 and 63, multipled by gain 64, and outputted.
This type of modulator, however, has a problem that the usage amount of hardware becomes large because two FIR filters 51 and 52 having n-bits inputs must be implemented using multipliers.
In order to solve this problem, by changing the arrangement of respective functional blocks in the modulating device shown in FIG. 1 and allowing the modulating device to be operated in the sequence of the Walsh covering stage, the 1-bit PN Spreader, the 1-bit FIR Filter, the gain stage, the channel adder and the complex adder, although this structure has the same functions to the previous structure, it can reduce the usage amount of hardware to be implemented and use a 1-bit input FIR filter for 4-channel capable of the usage amount of hardware is reduced, instead of using n-bits input FIR filter having a large usage amount of hardware.
The present invention proposes a design technology for VLSI (Very Large Scale Integration) implementation of a 1-bit input FIR filter for 4-channel. Conventionally, a FIR filter design technology of a look-up table scheme for 2- channel has been employed.
FIG. 2 illustrates a construction of a conventional FIR filter device of a look-up table scheme for 2-channel.
As shown in FIG. 2, the FIR filter device includes I-channel 12-bits shift registers 70 and 71, Q-channel 12-bit shift registers 72 and 73, 6-bit 2×1 MUX 74 and 75, 256×11-bit look-up table ROM_0 and ROM_176 and 77, and an 11-bit adder 78. Because a 1-bit input data used in operation of the 48-tap 1:4 interpolation FIR filter is twelve (12), I-channel and Q-channel 12-bit shift registers 70, 71, 72 and 73 are required. Twelve binary filter inputs of the I-channel and the Q-channel are inputted to twelve bit shift registers, respectively.
These inputs are divided into two groups each of which includes 6 bits and IR1[5:0] 70 and QR1 [5:0] 72 are multiplexed by a 6-bit MUX 74. Also, 2-bit group selection clock is attached to the result so as to address a 256×11-bit ROM_076. In the same way, IR2[5:0] 71 and QR2[5:0] 73 are multiplexed by a 6-bit MUX 75 and 2-bit group selection clock is then attached to the result so as to address a 256×11-bit ROM_177.
Two look-up table outputs from the two ROM 76 and 77 are added in a 11 -bit adder 78, which then produces a final filter output. Because these procedures are sequentially performed for four coefficient groups, 1:4 interpolation filter operation is performed by which four-time outputs are created for one-time filter input, and the inputs, I-channel and Q-channel the filter are alternately selected by means of the multiplexers 74 and 75. Therefore, the filter outputs of the I-channel and the Q-channel are outputted in a multiplexed form.
This type of the 48-tap 1:4 interpolation FIR filter can have the following filter coefficient groups.
G0 = {C0, C4, C8, C12, C16, C20, C24, C28, C32, C36, C40, C44}G1 = {C1, C5, C9, C13, C17, C21, C25, C29, C33, C37, C41, C45}G2 = {C2, C6, C10, C14, C18, C22, C26, C30, C34, C38, C42, C46}G3 = {C3, C7, C11, C15, C19, C23, C27, C31, C35, C39, C43, C47}
That is, four coefficient groups G0, G1, G2 and G3 are used for the filter operation. The number of the output value that can be produced by filter operation per each group is 212. Therefore, assuming that the output value of the look-up table is 11-bits, it is required that the size of the look-up table be 212×11-bit per respective coefficient groups. For the purpose of the efficiency of the design area, if the size of the filter input shift register becomes 6 bits by dividing it by two and two look-up tables and one adder are used, a look-up table having the size of 2×26×11-bit can be designed as shown in FIG. 2. As a result, the size of the final look-up table that performs four coefficient group operations becomes 2×4×26×11=2×256×11-bit.
Upon implementation of 48-tap 1:4 interpolation FIR filter using this design technology of a look-up table scheme for 2-channel, the hardware structure may be simplified. However, if two output filter operation is to be performed in order to simultaneously transmit produce outputs from two filters, a read operation on the memory must be performed twice faster. In addition, in order to design a 108-tap 1:4 interpolation FIR filter for 4-channel, the operating frequency of the filter must be faster by four times. Also, as the size of the look-up table ROM requires 2×4×2—5 ×11-bit, the size of the look-up table becomes greater at least 100 times than that of the 48 tap.
As such, if the 108-tap 1:4 interpolation FIR filter is implemented using a conventional technology, the size of a filter design area and the frequency of an operating frequency are increased since the number of a filter tap and the number of channel to be supported are increased.